1. Technical Field
Embodiments of the invention relate to systems and methods for transferring synchronous digital signals across an asynchronous boundary.
2. Description of the Background
In systems using digital circuitry, two functional blocks or subsystems operating in two different timing domains often communicate with one another. When these two blocks operate in synchrony with a single digital clock signal, transfer of digital data between the two blocks does not present a problem. However, when two digital subsystems operate in synchrony with different clock signals, any digital data signals traveling between the subsystems should be synchronized in some manner to avoid data errors.
If, for example, two digital subsystems operate in synchrony with different clocks, the system should resynchronize the digital data signals traveling from one subsystem to the other subsystem. In other words, if data signals travel from a first subsystem in an external clock domain to a second subsystem in an internal clock domain, the digital system should resynchronize the data signals with an internal clock signal at the asynchronous boundary. Similarly, if data signals travel an internal clock domain to an external clock domain, the digital system should resynchronize the data signals with an external clock signal at the asynchronous boundary. Without such resynchronization, a hardware “metastability” problem can result in clocked devices of the receiving subsystem, thereby producing invalid logic results. Metastability generally refers to a circuit or system that has an unstable and transient, but relatively long-lived state. The problem of metastability is well known in the art, and can be illustrated, for example, by operation of a bistable latch.
A bistable latch requires the coincident occurrence of two pulses, e.g., a data pulse and a clock pulse, to change the state of the latch. In a bistable latch, a “metastable” state can occur when the two actuating pulses do not overlap sufficiently in time to permit the bistable latch to completely switch from one stable state to the other. With insufficient overlap, such as setup time violation or hold time violation can occur when a clock pulse is poorly synchronized with a data pulse, the bistable latch output can move from one stable level to the other and then back again. In the context of two distinct clock domains, the metastable latch problem occurs when a clock pulse from one domain overlaps insufficiently with a data pulse synchronized to a clock pulse from another domain.
Stated another way, a clocked bistable latch can malfunction if the data input changes during the setup-time interval preceding a clock pulse. As long as the clocked bistable latch makes some decision upon receipt of the active edge of the clock pulse, the circuit incorporating the latch will operate properly. An incoming transition edge of a data signal should occur before a transition edge of a clock signal to the latch. However, if the input changes at a particularly bad time within the setup-time, the clocked bistable latch can hover at the logic threshold or the clocked bistable latch can go into one state and then switch back to the other state. Stated yet another way, a clocked bistable latch can malfunction if the data input changes during the hold-time interval following a clock pulse.
One method of determining whether a problem in data synchronization across asynchronous boundaries will occur is to employ a higher frequency clock. The higher frequency clock may then determine the relationship between clocks in each of two asynchronous domains. However, a higher frequency clock requires circuitry to have less margin of error, thereby making associated circuitry more difficult to design.
Thus, a need exists for systems and methods of transferring synchronous digital signals across an asynchronous boundary separating a transmitting subsystem and a receiving subsystem. A need exists for a system that avoids data transitions during the setup times for clocked devices within the receiving subsystem. Moreover, there is a need for systems and methods to compensate for clock/data synchronization errors in general.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.